Field of the Invention
Generally, the present disclosure relates to the manufacture of sophisticated semiconductor devices, and, more specifically, to various methods and structures for using offset metal power rails for improved standard cells for improved cell routability for manufacturing semiconductor devices.
Description of the Related Art
The technology explosion in the manufacturing industry has resulted in many new and innovative manufacturing processes. Today's manufacturing processes, particularly semiconductor manufacturing processes, call for a large number of important steps. These process steps are usually vital, and therefore, require a number of inputs that are generally fine-tuned to maintain proper manufacturing control.
The manufacture of semiconductor devices requires a number of discrete process steps to create a packaged semiconductor device from raw semiconductor material. The various processes, from the initial growth of the semiconductor material, the slicing of the semiconductor crystal into individual wafers, the fabrication stages (etching, doping, ion implanting, or the like), to the packaging and final testing of the completed device, are so different from one another and specialized that the processes may be performed in different manufacturing locations that contain different control schemes.
Generally, a set of processing steps is performed on a group of semiconductor wafers, sometimes referred to as a lot, using semiconductor-manufacturing tools, such as exposure tool or a stepper. As an example, an etch process may be performed on the semiconductor wafers to shape objects on the semiconductor wafer, such as polysilicon lines, each of which may function as a gate electrode for a transistor. As another example, a plurality of metal lines, e.g., aluminum or copper, may be formed that serve as conductive lines that connect one conductive region on the semiconductor wafer to another.
In this manner, integrated circuit chips may be fabricated. In some cases, integrated circuit or chips may comprise various devices that work together based upon a hard-coded program. For example, application-specific integrated circuit (ASIC) chips may use a hard-coded program for various operations, e.g., boot up and configuration processes. The program code, in the form of binary data, is hard-coded into the integrated circuit chips.
When designing a layout of various devices with an integrated circuits (e.g., CMOS logic architecture), designers often select pre-designed functional cells comprising various features (e.g., diffusion regions, transistors, metal lines, vias, etc.) and place them strategically to provide an active area of an integrated circuit. One challenge of designing a layout is accommodating ever-increasing density of cell components and still maintain routability for connecting various components of the cells. This is increasingly a challenge as dimensions of these components get smaller, such as for 10 nm or lower integrated circuit designs.
The pre-designed functional cells are often used to design transistors, such as metal oxide field effect transistors (MOSFETs or FETs). A FET is a device that typically includes a source region, a drain region, a channel region that is positioned between the source region and the drain region, and a gate electrode positioned above the channel region. Current flow through the FET is controlled by controlling the voltage applied to the gate electrode. If a voltage that is less than the threshold voltage of the device is applied to the gate electrode, then there is no current flow through the device (ignoring undesirable leakage currents, which are relatively small). However, when a voltage that is equal to or greater than the threshold voltage of the device is applied to the gate electrode, the channel region becomes conductive, and electrical current is permitted to flow between the source region and the drain region through the conductive channel region.
To improve the operating speed of FETs, and to increase the density of FETs on an integrated circuit device, device designers have greatly reduced the physical size of FETs over the years. More specifically, the channel length of FETs has been significantly decreased, which has resulted in improving the switching speed of FETs. However, decreasing the channel length of a FET also decreases the distance between the source region and the drain region. In some cases, this decrease in the separation between the source and the drain makes it difficult to efficiently inhibit the electrical potential of the channel from being adversely affected by the electrical potential of the drain. This is sometimes referred to as a so-called short channel effect, wherein the characteristic of the FET as an active switch is degraded.
There are essentially two types of FETs: planar FETs and so-called 3D devices, such as an illustrative finFET device, which is a 3-dimensional structure. More specifically, in a finFET, a generally vertically positioned, fin-shaped active area is formed and a gate electrode encloses both of the sides and the upper surface of the fin-shaped active area to form a trigate structure so as to use a channel having a 3-dimensional structure instead of a planar structure. In some cases, an insulating cap layer, e.g., silicon nitride, is positioned at the top of the fin and the finFET device only has a dual-gate structure.
FinFET designs use “fins” that may be formed on the surface of a semiconductor wafer using selective-etching processes. The fins may be used to form a raised channel between the gate and the source and drain of a transistor. The gate is then deposited such that it wraps around the fin to form a frigate structure. Since the channel is extremely thin, the gate would generally have a greater control over the carriers within. However, when the transistor is switched on, the shape of the channel may limit the current flow. Therefore, multiple fins may be used in parallel to provide greater current flow for increased drive strength.
FIG. 1 illustrates a stylized cross-sectional depiction of a state-of-the-art finFET device. A finFET device 100 illustrated in FIG. 1 comprises a plurality of “fins” 110. The semiconductor device may be position to a vertical orientation, creating one or more fins 110. The source and drain of the finFET are placed horizontally along the fin. A high-k metal gate 120 wraps over the fin, covering it on three sides. The gate 120 defines the length of the finFET device. The current flow occurs along an orthogonal crystal plane in a direction parallel to the plane of the semiconductor wafer. The electrically significant height of the fin (labeled H) is typically determined by the amount of oxide recess in the fin reveal step and hence is constant for all fins 110.
The thickness of the fin (labeled Tfi) determines the short channel behavior of the transistor device and is usually small in comparison with the height H of the fin 110. The pitch (labeled P) of the fins is determined by lithographic constraints and dictates the wafer area to implement the desired device width. A small value of the pitch P and a large value of the height H enable a better packing of the devices per square area resulting in a denser design, or more efficient use of silicon wafer area.
The scaling down of integrated circuits coupled with higher performance requirements for these circuits have prompted an increased interest in finFETs. FinFETs generally have the increased channel widths, which includes channel portions formed on the sidewalls and top portions of the fins. Since drive currents of the finFETs are proportional to the channel widths, finFETs generally display increase drive current capabilities.
The ultimate goal in integrated circuit fabrication is to accurately reproduce the original circuit design on integrated circuit products. Historically, the feature sizes and pitches employed in integrated circuit products were such that a desired pattern could be formed using a single patterned photoresist masking layer. However, in recent years, device dimensions and pitches have been reduced to the point where existing photolithography tools, e.g., 193 nm wavelength immersion photolithography tools, cannot form a single patterned mask layer with all of the features of the overall target pattern. Accordingly, device designers have resorted to techniques that involve performing multiple exposures to define a single target pattern in a layer of material. One such technique is generally referred to as multiple patterning, e.g., double patterning. Generally speaking, double patterning is an exposure method that involves splitting (i.e., dividing or separating) a dense overall target circuit pattern into two separate, less-dense patterns. The simplified, less-dense patterns are then printed separately on a wafer utilizing two separate masks (where one of the masks is utilized to image one of the less-dense patterns, and the other mask is utilized to image the other less-dense pattern). Further, in some cases, the second pattern is printed in between the lines of the first pattern such that the imaged wafer has, for example, a feature pitch which is half that found on either of the two less-dense masks. This technique effectively lowers the complexity of the photolithography process, improving the achievable resolution and enabling the printing of far smaller features than would otherwise be impossible using existing photolithography tools.
The Self-Aligned-Double-Patterning (SADP) process is one such multiple patterning technique. The SADP process may be an attractive solution for manufacturing next-generation devices, particularly metal routing lines on such next-generation devices, due to better overlay control that is possible when using an SADP process. In SADP processes, metal features that are defined by mandrel patterns are referred to as “mandrel metal,” while metal feature that are not defined by mandrel patterns are called “non-mandrel metal.” Further, SADP processes generally have a high tolerance for overlay errors. Therefore, SADP processes have been increasingly adopted for metal formation in higher resolution designs, such as 10 nm designs.
Another example of multiple pattern techniques is the lithography-etch-lithography-etch (LELE) process, which generally involves creating the ultimate or desired target pattern in a hard mask material by performing two lithography and two etch processes. In an LELE double patterning process, a first photoresist layer is formed above a hard mask layer. Thereafter, the first photoresist layer is exposed during a first exposure process and subsequently developed to define a first patterned photoresist mask. Next, an etching process is performed through the first patterned photoresist mask on the hard mask layer to transfer the pattern in the first patterned photoresist mask to the hard mask layer. The first patterned photoresist mask is then removed from the now partially patterned hard mask layer. Next, a second photoresist layer is formed above the partially patterned hard mask layer. The second photoresist layer is then exposed during a second exposure process (using a different reticle) and subsequently developed to define a second patterned photoresist mask. An etching process is then performed through the second patterned photoresist mask on the partially patterned hard mask layer to transfer the pattern in the second patterned photoresist mask to the partially patterned hard mask layer. This latter etching process results in a final patterned hard mask layer having the desired target pattern. The second patterned photoresist mask is then removed. The final patterned hard mask layer may then be used to pattern an underlying layer of material.
To use double patterning techniques, an overall target pattern must be what is referred to as double-patterning-compliant. In general, this means that an overall target pattern is capable of being decomposed into two separate patterns that each may be printed in a single layer using existing photolithography tools. Layout designers sometime speak of such patterns with reference to “colors,” wherein the first mask will be represented in an EDA tool using a first color and the second mask will be represented in the EDA tool using a second, different color. To the extent a layout is non-double-patterning-complaint, it is sometimes stated to present a “coloring conflict” between the two masks.
Designers often use pre-designed basic cells to form layouts of more complex cells comprising finFET devices. One example of a typical pre-designed functional cell is illustrated in FIG. 2. FIG. 2 illustrates a typical standard cell 200 for a 10 nm node design. Since there is a strong industry demand for dense standard cell library, designers have implemented cell libraries of less than 9-tracks (9 T), such as 10 nm, 8.75 T libraries. The cell 200 is an example of a multi-track 10 nm, 8.75 T cell, which may comprise a plurality of components that densely populate the cell 200. The cell 200 comprises a plurality of metal pins (230a-230c) (e.g., Metal-1 (M1) metal pins. The six metal pins 130a-130f are input pins. The cell 200 also includes an output “U-shaped” pin 220. The cell 200 includes a VDD metal formation 250 on a routing track 251, and a VSS metal formation 260 on another routing track 261.
In some examples, the metals pins 230A and 230B may be input pins, while the U-shaped pin 220 and the metal pin 230C may be output pins. Further, the cell 200 also includes a plurality of vertical semiconductor formations 270, e.g., gate formations for a transistor. A plurality of pin hit point 275 provides for routing of M2 metal formations. At the boundary of the cell 200, the metal VDD line 250 and the metal VSS line 260 are defined. In light of the VDD line 250, the VSS line 260, the output pins 220, 230C, the utilization of metal-2 layer (M2) tracks 240 to connect the various pins 230A-230B can cause the cell 200 to become very difficult to connect. This causes routing-congestion and causes the routing task to be more difficult.
Since finFETs are being defined using the standard cells, such as the cell 200, a 3-dimensional height is defined for the cells 200. With regard to finFET technology, the cell height is generally associated with the fin pitch that results in non-integer or non-half integer number of metal pitches, e.g., 8.75 T libraries. Generally, uniform fin pitch is preferable to uniform metal pitch. Thus, the cell height has to generally confirm to a uniform standard based upon the fin pitch. For example, the cell height of a 48 nm cell would be 8.75 T multiplied by 48 nm, which is 420 nm. For ten fins, the fin pitch would be 420 nm divided by 10 fins, which is 42 nm. Further, the cell 200 has a 60 nm metal-1 layer (M1) power rail. In this manner, the cell 200 uses up a significant amount of real estate due to the width of the M1 VDD and VSS power rails.
Further, in the state-of-the-art, the metal-2 (M2) VDD and VSS power rails are often used to improve IR drop on power rails and thus improve circuit reliability. In the state-of-the-art, the M2 VDD and VSS power rails are symmetrically positioned about the cell boundary track, as illustrated in FIG. 3. FIG. 3 illustrates a stylized, simplified depiction of a portion of a cell 300 having metal-2 (M2) tracks and M2 power rails. In the example of FIG. 3, the M2 tracks on which the M2 power rails are formed overlaps with the cell boundaries 310, 320. Symmetrically about the 1st cell boundary 310 and M2 track, a non-mandrel metal M2 formation (350) is defined. Similarly, symmetrically about the 2nd cell boundary 320 and M2 track, a mandrel metal M2 formation (360) is defined.
The distance between the 1st cell boundary 310 and the top edge of the M2 metal 350 is “a,” which is the same distance between the 1st cell boundary 310 and the bottom edge of the M2 metal 350. Similarly, between the 2nd cell boundary 320 and the top edge of the M2 metal 360 is “a,” which is the same distance between the 2nd cell boundary 320 and the bottom edge of the M2 metal 360. The cell 300 includes a M2 routing tracks 340 that is 90 nm away from the 1st cell boundary 310, wherein the distance between the M2 tracks 340 is 48 nm.
FIG. 4 illustrates a stylized depiction of a typical grouped cell-pair including non-mandrel and mandrel boundary metal formations. The cell pair 400 comprises two cells that are grouped together, a 1st cell 401 and a 2nd cell 402. The cells 401, 402 are 10 nm, 8.75 T cells. Thus, on cell 401, there are eight horizontal tracks on which alternative mandrel and non-mandrel metal formations are defined.
A non-mandrel M2 metal formation 450 is defined symmetrically about a 1st boundary track 403. A mandrel M2 metal formation 460 is defined symmetrically about a 2nd boundary track 404. The non-mandrel power rail 450 and the mandrel power rail 460 are respectively coupled to VSS M1 power rail 455 and the VDD M1 power rail 465 using vias 490.
The non-mandrel M2 metal formation 450 followed by a mandrel M2 metal formation 485A, followed by a non-mandrel M2 metal 480A on the next track 440, followed by a mandrel M2 metal formation 485B on a subsequent track 440, followed by a non-mandrel M2 metal 480B, followed by a mandrel M2 metal 485C, and followed by a non-mandrel 480C. Finally, on the 2nd cell boundary 404, the wide mandrel M2 power rail 460 is defined symmetrically about the boundary 404, above a M1 power rail 465. Below the M2 power rail 460, on the next M2 track (in the 2nd cell 402), a non-mandrel M2 metal 480D is defined. In this manner, mandrel and non-mandrel M2 metal formations are alternated on the M2 tracks 440 and the cell boundaries 403, 404 in order to avoid color mismatch errors. For example, if instead of the non-mandrel metal 480D, a mandrel metal were defined, a color conflict error would occur.
Among the problems associated with the state-of-the-art includes the fact that the relatively large width of the power rails 450, 460 cause a reduction in one M2 routing track, which causes routing inefficiencies. Although the track grid on both sides of the cell boundary is larger than the default grid, there is insufficient space to insert an additional route track. That is, only six M2 routing tracks are available in each of the cells 401, 402. Even if various components of the cell pair 400 were to be reduced, the loss of the M2 routing track would not be overcome.
Other problems associated with the state-of-the-art includes the fact that wide M2 metal formations are required for both mandrel and non-mandrel metals (i.e., the power rails). This can cause poor mandrel printability on the top portion and the bottom portion of the cells. Further, the current designs of the cells 401, 403 cause the need for having M2 power rails to be of mandrel and non-mandrel metals. It would be more desirable to have design that comprises power rails that are all of mandrel metals. Further, it would be desirable to provide increased routing resources to efficiently route ever-increasing congestion of pre-defined cells. Therefore, as described above, there are various inefficiencies, errors, and other problems associated with the state-of-art.
The present disclosure may address and/or at least reduce one or more of the problems identified above.